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The high drain-effect transistor characteristic observed after hot-carrier injection and trapping in the oxide has been found to be due to the uneven trapped-carrier distribution near the drain, which causes the threshold voltage to vary as a function of drain voltage. A discussion of the role and effects of both electron and hole injection is presented. The nonlinear distribution of carriers trapped in the gate oxide is described. One result is that the nonuniform surface band bending causes the subthreshold leakage to be an exponential function of the drain voltage. The combined increase in threshold voltage, subthreshold leakage, and a decrease in subthreshold slope will translate into slower circuit speed and higher standby power dissipation [37] in CMOS circuits. An experimental model of the mean time to failure, for NMOS devices fabricated with two different source-drain diffusions, is also presented. For the first time, the model has been extended to include the channel-length dependence. The model assumes a reliability criterion of less than a 10-mV threshold-voltage shift in 100 000 h of operation. Experimental results and subsequent calculations show that for 350-Å gate-oxide devices at 5.0 V operation, 2.5 µm is the minimum electrical channel-length device which can be fabricated using a traditional source-drain process. Conversely, submicrometer electrical channel-length devices can be fabricated using an arsenic-phosphorous "graded" source-drain process, even at 5.5-V operation.
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Chen et al. (1985) studied this question.
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