Theoretical proposal for a multifunctional transistor using a 2D ferroelectric junction, suggesting innovative nanoelectronics applications.
A defining challenge for next-generation nanoelectronics is integrating diverse functionalities within a single device while strictly minimizing power consumption. Two-dimensional (2D) ferroelectrics, with their atomic-scale nonvolatility, offer a promising platform for such architectural innovation. Here, we theoretically propose a multifunctional single-transistor (1T) architecture embedding a 2D ferroelectric tunneling junction at the source–channel interface. Polarization reversal deterministically drives a nonvolatile band rearrangement, toggling the interface between a gapless type-III and a gapped type-I/II alignment. Demonstrated in an Al2S3/WTe2 device example, this mechanism seamlessly unifies dual electrical merits: the type-III alignment facilitates cold-source injection for an ultrasteep subthreshold swing of 28.3 mV/dec, while the polarization-induced barrier delivers a widely tunable, giant tunneling electroresistance ratio of up to 109. Exploiting these traits, we demonstrate 1T logic-in-memory operation potential, including a nonvolatile logic gate and a conditional readout secure memory. This paradigm provides a compelling theoretical foundation for highly integrated and low-power nanoelectronics.
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Yang et al. (2026) studied this question.
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