FFT scaling in Domino CMOS gates

The switching delay of a Domino CMOS gate can be reduced by up to 30% by scaling the NFET chain so that th FET closest to the ground is the largest, with FET size decreasing monotonically from ground to output. The technique is most effective when applied to complex gates, such as those found in a carry look-ahead circuit. The same technique has application to other MOS circuits including NMOS circuits.