What question did this study set out to answer?

To systematically analyze the architectural designs, performance bottlenecks, and trade-offs of FPGA-based accelerators for Fully Homomorphic Encryption (FHE) developed between 2011 and 2025.

August 16, 2026ACM Transactions on Reconfigurable Technology and Systems

Hardware Acceleration of Fully Homomorphic Encryption: A Comprehensive Review of FPGA Implementations

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Authors

LGLingyu Gong FMFarhad Merchant

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Overview

Systematic review reveals critical bottlenecks and architectural trade-offs in FPGA-based encryption acceleration, highlighting paths toward practical algorithm-hardware co-design.

Key Points

To systematically analyze the architectural designs, performance bottlenecks, and trade-offs of FPGA-based accelerators for Fully Homomorphic Encryption (FHE) developed between 2011 and 2025.
Reviewed FPGA-based FHE accelerator architectures published across the literature between 2011 and 2025.
Developed a unified analytical framework modeling computation and data movement to evaluate heterogeneous designs via roofline performance analysis.
Accelerator performance is jointly limited by arithmetic parallelism, memory bandwidth, data reuse, and communication overhead.
Designs with poor data reuse or key delivery bottlenecks remain memory-bandwidth-bound, whereas batched streaming architectures and kernel-level designs shift the limitation to compute capacity.
Identified primary design challenges in memory hierarchy, bandwidth utilization, communication efficiency, and cross-platform scalability.

Cite This Study

Gong et al. (2026) studied this question.

synapsesocial.com/papers/6a817a4cf2fb91fc834ae0d4 https://doi.org/10.1145/3840385

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August 16, 2026ACM Transactions on Reconfigurable Technology and Systems

Hardware Acceleration of Fully Homomorphic Encryption: A Comprehensive Review of FPGA Implementations

View Full Paper

Ask AI

Bookmark

Authors

LGLingyu Gong FMFarhad Merchant

Discussion

Member takes

Overview

Systematic review reveals critical bottlenecks and architectural trade-offs in FPGA-based encryption acceleration, highlighting paths toward practical algorithm-hardware co-design.

Key Points

To systematically analyze the architectural designs, performance bottlenecks, and trade-offs of FPGA-based accelerators for Fully Homomorphic Encryption (FHE) developed between 2011 and 2025.
Reviewed FPGA-based FHE accelerator architectures published across the literature between 2011 and 2025.
Developed a unified analytical framework modeling computation and data movement to evaluate heterogeneous designs via roofline performance analysis.
Accelerator performance is jointly limited by arithmetic parallelism, memory bandwidth, data reuse, and communication overhead.
Designs with poor data reuse or key delivery bottlenecks remain memory-bandwidth-bound, whereas batched streaming architectures and kernel-level designs shift the limitation to compute capacity.
Identified primary design challenges in memory hierarchy, bandwidth utilization, communication efficiency, and cross-platform scalability.

Cite This Study

Gong et al. (2026) studied this question.

synapsesocial.com/papers/6a817a4cf2fb91fc834ae0d4 https://doi.org/10.1145/3840385

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