The design and implementation of a very low supply voltage/low power /spl Delta//spl Sigma/ modulator is presented. It is based on the switched-opamp technique, which allows low voltage operation with a standard process and without voltage multiplication. The design methodology is illustrated with a second-order single-loop /spl Delta//spl Sigma/ modulator. The chip is implemented in a 0.7-/spl mu/m CMOS process with standard threshold voltages. The power supply is 1.5 V and the power dissipation is only 100 /spl mu/W. The measured dynamic range in the speech bandwidth of 300-3400 Hz is 12 b. The total harmonic distortion (THD) is lower than -72 dB.
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Peluso et al. (1997) studied this question.
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