Ultra‐Low Power 3D Ferroelectric Memory Using Atomically Thin Edge Electrode

This is the authors' abstract. We don't add key points for this paper.

The growing demand for 3D‐stacked high‐bandwidth memory in AI accelerators highlights the need for novel chip architectures to overcome data transfer bottlenecks. However, these advanced systems face significant challenges, including heat buildup from their compact designs and a limited number of memory stacks due to stack height constraints. Here, A two‐terminal, 3D vertical ferroelectric memory device is reported using a 10 nm thick Hf 0.5 Zr 0.5 O 2 ferroelectric layer integrated with an atomically thin (≈3 Å) graphene planar electrode, making it one of the thinnest ferroelectric memory devices. This ultra‐thin structure allows for more memory stacks within the same total height, significantly enhancing device integration. Notably, the ferroelectric diode's high current density coupled with the integration of an ultrathin electrode, enable an exceptionally low energy sub‐fj level switching (≈0.85 fJ at 1nA current) which can be adjusted to diverse application requirements. Endurance tests confirm stable operation over 10 5 switching cycles, with retention time exceeding 10 5 s. It achieves high intrinsic nonlinearity (≈201) by interchanging Schottky and ohmic contacts, enabling self‐selection and eliminating the need for an additional selector device. Statistical analysis of over a hundred devices reveals consistent switching behavior, high power efficiency, and reliable read operations, highlighting their potential for integration into data‐intensive computing systems.