Mask erosion during dry etching of deep features in III-V semiconductor structures

Erosion and changes in the sidewall smoothness of masking layers commonly used as dry etch masks for III-V semiconductors have been studied for Cl 2- , F 2- and CH 4 /H 2 -based discharges. A particular problem with photoresist masks is the introduction of sidewall roughness which is transferred into the underlying dielectric or semiconductor. Distortion of the resist mask also occurs during high DC bias dry etching, leading to feature widths wider than the original mask dimension. Both of these phenomena are minimized with the use of low ( approximately 100 V DC) self-bias during the etching. Dielectric layers such as SiO 2 display erosion and faceting of the mask edges during extended high-bias dry etching and for small (<or=1 mu m) feature widths this can lead to trenching at the base of the sidewalls. Metal-based (Al, Ti/Au) masks are much more resistant to erosion and appear to be favoured when etching deep (>2 mu m) features into both GaAs and InP.