A 0.18-/spl mu/m 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)

A nonvolatile 64-Mb 1T1R phase-transition random access memory (PRAM) has been developed by fully integrating chalcogenied storage material (GST: Ge/sub 2/Sb/sub 2/Te/sub 5/) into 0.18-/spl mu/m CMOS technology. To optimize SET/RESET distribution, 512-kb sub-array core architecture was proposed, featuring meshed ground line and separated SET/RESET control schemes. Random read access time, random SET and RESET write access times were measured to be 60 ns, 120 ns, and 50 ns, respectively, at 3.0-V supply voltage with 30/spl deg/ C.