Product development and yield enhancement through failure analysis of integrated circuits with scanning capacitance microscopy

The application of scanning capacitance microscopy (SCM) to failure analysis of integrated circuits is described. Both top-down (parallel to the wafer surface) and cross-sectional SCM measurements were performed on product lots containing yield-limiting failures identified with electrical testing. The SCM images of functioning devices were compared with those of failed devices to note any differences in free carrier distributions. Using this approach, the root causes of failures in two different product lots—one bulk Si technology and one silicon-on-insulator technology—were identified. These two examples are described in detail, as well as the subsequent corrective actions taken to improve yield.