Scanning capacitance spectroscopy: An analytical technique for pn-junction delineation in Si devices

Scanning capacitance spectroscopy (SCS), a variant of scanning capacitance microscopy (SCM), is presented. By cycling the applied dc bias voltage between the tip and sample on successive scan lines, several points of the high-frequency capacitance–voltage characteristic C(V) of the metal–oxide–semiconductor capacitor formed by the tip and oxidized Si surface are sampled throughout an entire image. By numerically integrating dC/dV, spatially resolved C(V) curves are obtained. Physical interpretation of the C(V) curves is simpler than for a dC/dV image as in a single-voltage SCM image, so that the pn junction may be unambiguously localized inside a narrow and well-defined region. We show SCS data of a transistor in which the pn junction is delineated with a spatial resolution of ±30 nm. This observation is consistent with the conclusion that SCS can delineate the pn junction to a precision comparable to the Si depletion width, in other words, the actual size of the electrical pn junction. A physical model to explain the observed SCS data near the pn junction is presented.