Gateless 1T-DRAM for cryogenic memory applications

Cryogenic memory has emerged as a key technology for quantum-computing systems. In this Letter, a gateless one-transistor DRAM (1T-DRAM) operation is demonstrated at cryogenic temperatures. As the temperature decreases, the latch window expands from 0.26 V at 300 K to 2.26 V at 4 K, resulting in stable memory operation with a large sensing margin of 414 μA at 4 K. Suppressed Shockley–Read–Hall recombination at cryogenic temperatures improves static retention exceeding 500 s at 77 and 4 K, with dynamic retention exceeding 1000 s. These results demonstrate the potential of gateless 1T-DRAM for high-density cryogenic memory applications.