Answers are grounded in this paper and cite their sources.
An instruction window that can tolerate latencies to DRAM memory is prohibitively complex and power hungry. To avoid having to build such large windows, runahead execution uses otherwise-idle clock cycles to achieve an average 22 percent performance improvement for processors with instruction windows of contemporary sizes. This technique incurs only a small hardware cost and does not significantly increase the processor's complexity.
No takes yet. Share an insight, caveat, or question.
Mutlu et al. (2003) studied this question.
Synapse has enriched 10 related papers. Consider them for comparative context: