Negative differential conductivity and carrier heating in gate-all-around Si nanowire FETs and its impact on CMOS logic circuits

In this paper, we present a fully-coupled and self-consistent continuum based three-dimensional numerical analysis to understand hot carrier and device self-heating effects for device-circuit co-optimization in Si gate-all-around nanowire FETs. We employ three-moment based energy transport formulations and two-dimensional quantum confinement effects to demonstrate negative differential conductivity in Si nanowire FETs and assess its impact on a CMOS inverter and three-stage ring oscillator. We show that strong two-dimensional quantum confinement yields volume inversion conditions in Si nanowire FETs and surround gate geometry enables better short-channel effect control. We find that hot carrier and self-heating effects can degrade ON-state current in Si nanowire FETs and severely limit the logic circuit performance due to the introduction of higher signal propagation delays.