Electronic states at the interface between indium tin oxide and silicon

Electronic properties and thermal stability of interfacial states between indium tin oxide (ITO) and monocrystalline silicon (Si) have been investigated. ITO films with thicknesses of about 300 nm were deposited by dc magnetron sputtering on n- and p-type (100) Si at room temperature. The samples were then annealed for 30 min at different temperatures in the range 100–600 °C, and the ITO-Si junction was found to exhibit rectifying behavior. Current-voltage (IV), capacitance-voltage (CV), and deep-level transient spectroscopy (DLTS) measurements have been used to electrically characterize the ITO-Si interface. DLTS measurements on p-type Si samples reveal a dominant hole trap at around 0.37 eV above the valence band edge. In the n-type samples, a broad band of electron traps occur in the range 0.1-0.2 eV below the conduction band edge. These electron traps display wide DLTS peaks, indicating a band of electronic energy levels rather than well-defined states originating from isolated point defects. All the traps in both the p- and n-type samples are found to be located near the ITO-Si interface. Investigations of the thermal stability of the observed electronic states show that the dominant hole trap anneal out after 30 min at 250 °C, while the dominant electron traps can be stable up to 500 °C. IV and DLTS measurements demonstrate a clear correlation between the annealing of the dominant electronic states and increase in the junction rectification.