Key result
The proposed IPFM core implemented with TSMC 90 nm CMOS technology achieved an operation frequency of 62.5 MHz with only 9.8 K gate counts for estimating the spectrum of heart rate variability.
A low-cost, high-speed VLSI chip implementation of the IPFM model enables effective spectral estimation of heart rate variability.
May enable compact real-time HRV spectral hardware; leaves open clinical validation and integration.
Heart rate variability (HRV) can be used to assess autonomic control activities. Among the HRV analysis methods, the integral pulse frequency modulation (IPFM) model demonstrates the functional mechanism for the cardiac pacemaker that can explain the generation of heartbeats. In this study, the IPFM model was implemented into a low‐cost very‐large‐scale integration (VLSI) chip, and the active spectrum of HRV was then estimated by solving for the nerve‐modulation signal in the model based on the compressed sensing (CS) method. The proposed IPFM chip utilised a time‐sharing scheme for hardware resource sharing, a look‐up table to calculate the sine and cosine operations, and multiplexers to control the data flow. Furthermore, based on the hardware resource sharing scheme, the proposed chip achieved a low‐cost and high‐speed design. Implemented with TSMC 90 nm CMOS technology, the proposed IPFM core had an operation frequency of 62.5 MHz with only 9.8 K gate counts. The spectrum of HRV could be effectively estimated through the VLSI implementation of IPFM based on CS.
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Chen et al. (2018) studied Heart rate variability (HRV) analysis. VLSI implementation of the IPFM model based on compressed sensing was evaluated on Operation frequency and gate counts. The proposed IPFM core implemented with TSMC 90 nm CMOS technology achieved an operation frequency of 62.5 MHz with only 9.8 K gate counts for estimating the spectrum of heart rate variability.
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