Area and Thickness Scaling of Forming Voltage of Resistive Switching Memories

Based on probability analysis, this letter presents a simplified analytical model for the area and thickness scaling of forming voltage of resistive switching memories. The model is validated by experimental data and enables forming voltage projection. A switching resistor network model is employed to simulate the statistical distributions of forming voltage, which also confirms the analytical model. The increase of forming voltage at decreasing device area is undesirable for memory scalability. Local field enhancement may help to reduce both the magnitude of forming voltage and its area dependence.