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November 1, 1998IEEE Electron Device Letters

MOS transistors with stacked SiO/sub 2/-Ta/sub 2/O/sub 5/-SiO/sub 2/ gate dielectrics for giga-scale integration of CMOS technologies

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Authors

IKI.C. KizilyalliPalo Alto UniversityRHRu HuangPeking UniversityRRRob RoyBAE Systems (Sweden)

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Kizilyalli et al. (1998) studied this question.

synapsesocial.com/papers/6a8a82aea90c2f4c44fbc12chttps://doi.org/10.1109/55.728900
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