A general approach to compact threshold voltage formulation based on 2D numerical simulation and experimental correlation for deep-submicron ULSI technology development [CMOS]

A unified compact threshold voltage model is developed, which accounts for the normal and reverse short-channel effects with full range of body- and drain-bias conditions, and has been verified with experimental data down to 0.18 /spl mu/m. The model only has five process-dependent fitting parameters with a simple one-iteration extraction procedure, and can be correlated to process variables for aiding new deep-submicron technology development. The approach to the model formulation is original and general, and can be extended to other key device performance parameters.