A new refractory self-aligned gate technology for fabrication of field-effect transistors (FETs) with low gate resistance and improved breakdown voltage is described. The asymmetric-n+, planarised-gate process uses 1 μm optical lithography to produce 0.5 μm-gate-length FETs with very low gate resistance. The process is suitable for high-volume small-signal and power MMIC production.
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Geissberger et al. (1987) studied this question.
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