A 1.66 mV FOM Output Cap-Less LDO With Current-Reused Dynamic Biasing and 20 ns Settling Time

A fully integrated output capacitor-less, nMOS regulation FET low-dropout (LDO) regulator with fast transient response for system-on-chip power regulation applications is presented. The error amplifier (EA) consists of a differential cross-coupled common-gate (CG) input stage achieving twice the transconductance and unity-gain-bandwidth in comparison to a conventional differential common-source stage. The low input resistance of the CG EA improves stability of the LDO over a wide range of load currents. The LDO employs a currentreused dynamic biasing technique to further improve the load transient response, with no extra quiescent current. It is designed and fabricated in a 0.18-μm CMOS technology for an input voltage range of 1.6-1.8 V, and an output voltage range of 1.4-1.6 V. Measured undershoot is 158 mV and settling time is 20 ns for 9-40 mA load change in 250 ps edge-time with zero load capacitance. The LDO core consumes 130 μA of quiescent current, occupies 0.21 mm2die area, and sustains 0-50 pF of on-chip load capacitance.