Circuit techniques for a VLSI memory

This paper describes circuit techniques necessary for dynamic RAMs with high-packing density to implement submicron device technology. An on-chip error checking and correcting technique using bidirectional parity checking is proposed to reduce the soft error rate. In a sense-refresh amplifier, capacitor-coupled presenting is introduced to compensate for threshold imbalance. An on-chip supply voltage conversion is described as a solution for a hot carrier-injection problem. A 256K CMOS dynamic RAM has been designed and fabricated as a test vehicle for these techniques.