A Low-Dropout Regulator for SoC With Q-Reduction

A low-dropout regulator for SoC, with an advanced Q-reduction circuit to minimize both the on-chip capacitance and the minimum output-current requirement down to 100 muA, is introduced in this paper. The idea has been implemented in a standard 0.35-mum CMOS technology (VTHNap 0.55 V and |VTHP| ap 0.75 V). The required on-chip capacitance is reduced to 6 pF, comparing to 25 pF for the case without Q-reduction circuit. From the experimental results, the proposed regulator-circuit implementation enables voltage regulation down to a 1.2-V supply voltage, and a dropout voltage of 200 mV at 100-mA maximum output current.