Characterization and Modeling of 4H-SiC Lateral MOSFETs for Integrated Circuit Design

A new process in 4H-SiC is developed that features n-type buried and inversion channel lateral MOSFETs that are fabricated with several different channel lengths (2-8 μm) and widths (8-32 μm ) and characterized over a wide temperature range (25°C-225°C). It is shown that the on-resistance of enhancement-mode SiC MOSFETs reduces with temperature despite a reduction in inversion mobility because of the interaction of interface states with temperature. To enable integrated circuit development using the developed MOSFETs, their electrical characteristics are modeled over geometry and temperature using the industry standard PSP MOSFET model. A new mathematical formulation to describe the presence of the interface states is also developed and implemented in the PSP model, and excellent agreement is shown between measurement and simulation using the modified PSP model.