Power Reduction Techniques in Megabit DRAM's

Power dissipation in dynamic random-access memories (DRAM's) is described. Power reduction techniques are summarized and a comparison is made of NMOS and CMOS for individual circuits focusing on power dissipation for full- V/sub cc/ precharge and half- V/sub cc/ precharge, decoder, and clock generator. These results are then applied to actual 1-Mbit chips. The CMOS approach with a half-V/sub cc/ precharge is found to result in a power dissipation of just half that for NMOS, which is, verified through experiments on 1-Mbit CMOS and NMOS chips. Furthermore, from estimating power dissipation for DRAM chips larger than 1 Mbit, it is thought that the critical point for power-supply transition from the existing 5 V is around the 16-Mbit level.