A high-performance built-in error checking and correcting (ECC) technique applicable to megabit-level dynamic RAM (DRAM) chips is described. This technique, based on a bidirectional parity code, achieves high-speed error correction with a minimum increase in area. The impact of the technique on access time and chip overhead is discussed. Furthermore, effects on soft-error reduction and yield improvement are analytically investigated.
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J. Yamada (1987) studied this question.
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