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Hardware evaluation demonstrates a compact 8-bit substitution box with low delay in CMOS implementations, indicating high efficiency for lightweight cryptographic applications.
In this paper, a lightweight S‐box with acceptable cryptographic properties is presented. The proposed S‐box is designed using smaller S‐boxes. Here, we design an 8‐bit S‐box with a nonlinearity of 100 by combining three 4‐bit S‐boxes using SageMath. The 4‐bit S‐boxes have favorable hardware and cryptographic characteristics. By applying algebraic simplifications to the algebraic relations of these S‐boxes, we have arrived at optimized hardware structures for the 4‐bit S‐boxes. This ultimately leads to a reduction in hardware consumption and a decrease in the delay of the proposed 8‐bit S‐box. The proposed structure requires minimal hardware resources while preserving its cryptographic properties. The implementation results using 180‐ and 65‐nm CMOS technologies demonstrate that the proposed S‐box performs comparably in terms of area, delay, and AreaTime when compared to most other works. The proposed S‐box is area‐efficient, making it suitable for lightweight cryptographic applications.
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Bahram Rashidi (2026) studied this question.
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