Low-current blocking temperature writing of double barrier magnetic random access memory cells

A magnetic random access memory cell architecture is fabricated where the pinned layer is reversed by heating above a reduced blocking temperature with a current pulse crossing the junction, and cooled under an external applied field (word line), minimizing half-select switching of nonaddressed bits. In order to improve Joule heating and increase breakdown voltage, a double barrier structure was used, with a common antiferromagnetic layer (60 Å MnIr) two pinned 30 Å CoFe layers, and two free layers incorporating nanooxide structures. The blocking temperature was reduced to 120 °C. A TMR of 25% was achieved for both single barrier and double barrier tunnel junctions with resistance×area products of ∼40 Ω×μm2 and ∼280 Ω×μm2, respectively. Pinned layer writing allows the definition of a three-state memory, requiring, however, a destructive read out. A significant improvement of writing efficiency is observed with the double barrier structure. A 10 ns current pulse of 9 mA/μm2 is sufficient to heat the double barrier junctions above the blocking temperature and induce pinned layer switching.