Charge character of interface traps at the Si-SiO2 interface

Interface traps in the upper half of a silicon band gap are acceptorlike. This is based on analyses of the shift in capacitance-voltage curves due to positive bias-temperature aging of metal-oxide-semiconductor capacitors fabricated on n- and p-type substrates. The experimental results show that the interface traps in the upper half are generated without an increase in fixed oxide charges or interface traps in the lower half. The results also show that the flatband voltage shifts positively for n-type capacitors, while it does not shift for p-type capacitors.