Temperature formation of the inversion layer in metal-oxide-semiconductor structures: Theoretical model and application to the determination of minority-capture cross sections of the gold acceptor level in silicon

We study the formation of the inversion layer in metal-oxide-semiconductor (MOS) capacitors under reverse dc bias as the temperature is scanned from low (100-K) to high (400-K) values. It gives rise to a capacitance step on the capacitance-temperature (C-T) characteristics and to an artifact peak in the deep-level transient spectroscopy (DLTS) spectra. A theoretical simulation of the C-T characteristics, taking into account the generation of minority carriers via deep states in the bulk substrate and via interface states, is in good agreement with the experimental results. We describe accurately the evolution of the inversion charge from an exact determination of the depth limits in the space-charge region between which a single energy level behaves as a generation center. Moreover, we propose a method using C-T measurements, DLTS, and C-T simulations by our model to determine the minority-carrier capture cross section of bulk defects in the semiconductor substrate of the MOS capacitors. We successfully apply this method to determine the hole-capture cross section of the gold acceptor level in n-type silicon.