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An analogue CAD tool capable of simulating MOS circuit performance variance caused by intra‐die variability inherent to IC fabrication processes has been developed. the nucleus of this tool is a general, CAD‐compatible, MOS statistical model called SMOS which comprehends the effects of device geometry, circuit layout and transistor bias on parameter variance. an example of the model calculation procedure is presented to illustrate both the modelling algorithms and the process characterization data required by the statistical model. the statistical model is verified through experimental data which show excellent agreement with performance variances predicted by simulation. Implementations of the statistical model in two circuit simulation environments, SPICE and APLAC, are also described. Statistical analysis and simulation of two basic analogue subcircuits, the current mirror and the source‐coupled pair, are presented.
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Michael et al. (1992) studied this question.
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