Monolithic 2.1 Gbit/s decision circuit with a decision threshold ambiguity width of less than 10 mV

An Si bipolar monolithic decision circuit for practical use is developed using an improved circuit technique and super self-aligned process technology with the reliable 1.25 μm rule. The circuit consists of a slice amplifier, a master-slave D flip-flop and an output buffer. This circuit is capable of operating up to 2.1 Gbit/s with a decision threshold ambiguity width of less than 10 mV. In addition, a clock phase margin of 250 degrees and power dissipation of 640 mW at VEE=−6 V can be achieved.