Thinning of silicon-on-insulator wafers by numerically controlled plasma chemical vaporization machining

Silicon-on-insulator (SOI) wafers are semiconductor substrates that can be used in next-generation high-speed and low-power devices. An ultrathin SOI wafer with a SOI layer of less than 20 nm is required for the dynamic random access memory half-pitch node of 100 nm or lower. In this report, the thinning of the SOI layer by numerically controlled plasma chemical vaporization machining is described. A commercial 6 in. SOI wafer was used for the demonstration thinning. Spectroscopic ellipsometry was used to measure the thickness distribution of the SOI layer. The SOI layer thickness of ∼200±4 nm was successfully thinned to 13±2 nm.