A new four-quadrant CMOS analogue multiplier is presented which is based on the operation of MOS transistors in the saturation region and has simple circuit configuration and good linearity. The simulation result shows that less than 1% distortion can be obtained for input signals of 5.6 V peak to peak and supply voltages of ± 5 V.
No takes yet. Share an insight, caveat, or question.
Kim et al. (1992) studied this question.