Hot-carrier degradation in poly-Si lightly doped drain (LDD) thin-film transistors (TFTs) can be significantly reduced compared to that in single drain (SD) TFTs. Degradation for both types of TFTs was worst at the gate voltage corresponding to the largest substrate hole current. According to a power-time dependence law of Δ Gm max for both types of TFTs, the degradation is ascribable to interface state generation at the poly-Si/gate oxide interface and in the grain boundaries.
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Tango et al. (2002) studied this question.