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We report a merged n-HJFET/Pnp-HBT technology for high-speed circuits. This technology is based upon using the p+ junction gate of the n-HJFET as the emitter of the Pnp-HBT. The channel of the FET is used as the base and the p-buffer functions as the collector facilitating the fabrication of both devices from the same epilayer structure.
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Parikh et al. (1996) studied this question.
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