Fabrication of High Performance Low-Temperature Poly-Si Thin-Film Transistors Using a Modulated Process

A modulated process (MP) for the fabrication of low temperature processed (LTP) polysilicon thin-film transistors (poly-Si TFTs) using fewer processing steps but resulting in improved performance is investigated in this study. The modulated process is characterized by combining the solid-phase crystallization (SPC) step and the implant annealing into a single annealing step processed after the source/drain implantation. This is to say that the processing step of SPC is omitted, such that the SPC and implant annealing are conducted simultaneously. In this way, the process time is substantially shortened and the device performance is significantly improved. The improvement of device performance is presumably attributed to the larger poly-Si grain in the channel region processed by the MP scheme. In addition, the MP samples have a better -plasma passivation efficiency than the conventional process (CP) samples; this also implies that the MP samples contain larger grains in the channel regions than the CP samples. The electrical stress-induced degradation of device characteristics for the -plasma passivated MP samples is attributed to the carrier-induced metastable defects in the channel region.