Design of DC gate electric field redistribution under high drain voltage for high linearity, wide gain control range, and low C off in GaN dual-mode integrated devices

In this work, we propose and demonstrate a technique for optimizing linearity and off-state capacitance (Coff) in dual-mode integrated gallium nitride high-electron-mobility transistors with direct current (DC) gate bias control. In the dual-mode integrated high-electron-mobility transistor (HEMT), the large-resistance bias gate near the drain serves as a modulator for transconductance (gm) and off-state capacitance. It is shown that, in power amplifier mode, adjusting the DC gate bias redistributes the electric field, effectively reduces the peak field between the gate and drain, delays carrier velocity saturation, and mitigates self-heating effects, thereby significantly improving gm under high drain voltage. Measurements demonstrate that by optimizing the DC gate bias, both the output third-order intercept point (OIP3) and the gain of the dual-mode integrated HEMT are markedly enhanced. At 8 GHz and Vd = 50 V, increasing the DC gate bias from −2 to 28 V yields a tunable range of 12.1 dB and an OIP3 of 38.6 dBm. In switching mode, applying a negative DC gate bias introduces a series capacitance and reduces the radio frequency gate capacitance formed by the two-dimensional electron gas, resulting in an ultralow Coff of approximately 5 fF/mm. More importantly, this approach provides a new design degree of freedom: simply varying the DC level of the gate bias enables continuous tuning of the device's linearity, gain, and isolation.