Low‐Power Column‐Parallel Single‐Slope Analog‐to‐Digital Converter With Floating Inverter Amplifier for CMOS Image Sensors

This paper presents a low‐power column‐parallel single‐slope analog‐to‐digital converter that employs a floating inverter amplifier as the static comparator to address the power consumption issue of CMOS image sensors. In the proposed operating mode, voltage quantization is achieved with only a single charging and switching event, significantly reducing the energy consumption of the comparator. A fixed flip‐point structure is employed to eliminate the voltage variation of the floating power capacitor near the flip‐point caused by changes in the input common‐mode voltage, thereby resolving the issue of comparator output delay uncertainty. Additionally, to mitigate the impact of power supply noise and reduce the power consumption of the comparator, the floating inverter amplifier is biased in the deep subthreshold region with a large floating capacitor and transistors with small W/L ratios. A prototype of the CMOS column‐parallel SS ADC array was fabricated using a 110‐nm 1P4 M CMOS process. Experimental results show that the 10‐bit ADC achieves a differential nonlinearity (DNL) of 0.59/+0.48 LSB and an integral nonlinearity (INL) of 0.85/+1.28 LSB at a sampling frequency of 76.9 kHz. The power consumption of the comparator is 62.5 nW, and the column power consumption is 25.27 µW. Experimental results demonstrate that the comparator effectively reduces the power consumption of the SS ADC.