A low-power, low-offset, and power-scalable comparator suitable for low-frequency applications

Purpose This paper presents a novel low-power, low input offset rail-to-rail comparator that is suitable for a digital dominant successive approximation resistor analog-to-digital converter. The proposed comparator is based on traditional inverters cascaded to amplify analog signals and digital logic level conversion. The absence of a direct path between the high-swing output node and the input node restricts kickback noise.Design/methodology/approach The proposed circuit is designed and simulated using UMC 28 nm and 40 nm CMOS technology. The simulated power consumption using UMC 40 nm CMOS technology is 6.2084 μW at 1.1 V (330.8nW at 700 mV) supply voltage at the 2.5 MHz clock frequency. Similarly, simulated power consumption using UMC 28 nm technology is 0.04104μW at 900 mV (0.0097μW at 600 mV) and supply voltage operating at 66.66 MHz clock frequency with a resolution of a maximum of 12 bits, therefore, a reduction of more than 90% in power consumption observed by scaling technology node.Findings The conventional power-efficient clock-controlled latched comparator does not have a static current during the entire operation. The main drawbacks are the limited input range and the the kickback noise. However, a large voltage swing on the drain of a differential pair, due to this current feeding through a parasitic drain gate capacitor to the input node and the presence of source impedance, results in kickback noise. The performance of the ADC can be hampered by excessive kickback noise, which can eventually cause an incorrect comparator output. An inverter-based comparator is reported, where the input range is rail-to-rail and operates at moderate speed. Modern scaled technologies have better matching among transistors, i.e. matching of switching threshold voltage achieved by selecting suitable aspect ratios of transistors (cascaded inverters). Inverter-based dynamic comparators are inherently power-scalable and switching threshold voltage scales with supply voltage variation. Therefore, the amplification operation is not hampered by the reduction of the supply voltage.Originality/value The proposed architecture is compared with a set of existing hardware architectures to analyse various design metrics, such as low input offset, power scalability to maintain the resolution of the comparator, and low kickback noise.