Low-power Multi-Cauda Comparator Designed Using a Fragmentary Pre-charging Approach

To reduce the power consumption of a dynamic comparator, a unique fragmentary pre-charging technique is demonstrated in this paper. In essence, it permits the comparator to evaluate the output nodes not at full output swing but rather after pre-charging to a lower potential. The proposed comparator operates at a maximum frequency of 2.5 GHz, achieving an input offset voltage of 0.5 mV, consuming 367 nW average power. Comparative analysis with state-of-the-art techniques shows that the proposed comparator achieves 4× better energy efficiency with regard to the amount of energy per conversion and 20× better input offset voltage. Additionally, the effectiveness of the comparator is verified by incorporating it into a 10-bit flash-type analog-to-digital converter.