Performance Analysis of Fast & Power Efficient Dynamic Comparator Topologies

Comparator is an important block of ADCs. Dynamic comparators have replaced static comparators as these are fast and also address the issue of huge static power dissipation in static comparators. Therefore, ADCs, which require high speed and less power consumption, use dynamic regenerative comparators. These comparators are clock based and has two stages: a latch stage and a preamplifier stage. Fast operation, less power consumption, high accuracy, and less offset are some desirable features of a comparator. Any one topology of comparator cannot provide all these features. Thus, an effort has been made in this work to analyze performance of some topologies of dynamic comparators based on parameters like power, delay, slew rate and number of transistors. So, it is easy to select suitable comparator topology based on required application. This paper comprises of comparison between three topologies of dynamic comparators which are as follows: Shared charge reset technique based dynamic latched comparator (SCRDLC), Low-Power 1Volt supply Dynamic Comparator (LP1VSDC) and Cascode Cross-Coupled Stage High-Speed Dynamic Comparator (CCSHSDC). These comparators are simulated on Cadence Virtuoso simulation software using 45-nm technology.