February 14, 2024Journal of Circuits Systems and Computers

Review on High-Speed Dynamic Comparators for Analog to Digital Converters

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Dynamic comparators achieve high speed and low power consumption across topologies, though kickback noise and offset limit overall converter efficiency.
Simulation in 65 nm CMOS technology demonstrates that power delay product and delay determine overall performance limits in high-speed dynamic comparators.
Highlights from comparative design methodologies indicate that minimizing kickback noise and power delay product may enable optimized analog to digital converters.

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Implication

Review demonstrates high-speed dynamic comparator performance trade-offs in 65 nm CMOS technology, highlighting optimal topologies for analog-to-digital converters.

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Krishna et al. (2024) studied this question.

synapsesocial.com/papers/68e792dab6db643587704721 https://doi.org/10.1142/s021812662430006x

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Implication

Review demonstrates high-speed dynamic comparator performance trade-offs in 65 nm CMOS technology, highlighting optimal topologies for analog-to-digital converters.

Review on High-Speed Dynamic Comparators for Analog to Digital Converters

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Discussion

Implication

Cite This Study

Review on High-Speed Dynamic Comparators for Analog to Digital Converters

Key Points

Discussion

Implication

Cite This Study

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