A high-speed dynamic comparator with automatic dc offset compensation is proposed in this paper. The comparator is based on a double-tail topology and reduces the dc offset by a calibration circuit. Avoiding using the commonly used capacitive calibration, it can operate at a higher speed compared to other topologies. Designed in a CMOS 65nm technology node, it operates with 1 V supply voltage and clock speed at 10 GHz.
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Tsirmpas et al. (2024) studied this question.
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