An Enhanced Bulk-Driven Double-Tail Dynamic Comparator with Fast Discharge for Improved Speed and Energy Efficiency

Comparators are important components of low-voltage, high-speed analog-to-digital converters (ADCs). The double-tail dynamic comparator (DTDC) offers the best power-speed trade off, but suffers from unavoidable delay due to limited divergence of nodes and relatively slow latch regeneration. In this work, a Bulk-Driven Double-Tail Dynamic Comparator with Fast Discharge is proposed to improve the divergence between internal nodes and overall speed. The proposed design includes two extra transistors in the amplification stage for improved differential gain; in addition, an auxiliary discharge path controlled by clock is included that speeds up the discharge of internal nodes, thereby improving the voltage difference at the latch input leading to faster comparision. The circuit is implemented with a 180 nm CMOS technology and simulated in Cadence Spectre. The simulation results show a delay reduction of 20% compared to the conventional bulk-driven DTDC, while also showing competitive power consumption and fabrication robustness across process corners. The proposed design achieves a power-delay product of 0.82 fJ, a figure of merit (FOM) of 0.41 fJ/conversion, and stable offset of 10.99 mV. The simulation results show that the modified BD-DTDC architecture provides better speed and energy efficiency metrics, making it appropriate for high-speed, low-voltage ADC designs.