A Low-Offset and High-Speed Latch Comparator with Single Tail-Clocked Inverter Preamplifier for High Resolution Applications

Dynamic latch comparators (DLC) are among the most crucial building blocks in many analog mixed-signal circuits. This research report focuses on the design of an improved dynamic latch comparator for high-speed applications. The proposed circuit consists of a two-stage comparator, a preamplifier, and a latch. The preamplifier is an single tail clocked inverter-based amplifier. This will provide low power consumption, excellent kickback noise immunity and low input-referred offset. The latch stage, which is the main contribution, consists of complementary input transistors to improve gain before the decision, acting like a three-stage comparator. Moreover, a reset switch is added to set the precharge point to V dd /2, thereby improving comparison speed. The circuit is implemented in 65 nm CMOS technology with a 1 V power supply. The proposed circuit exhibits a low power delay product of 10.8 fJ, corresponding to an energy per comparison of 4.32 fJ/GHz, for a 2.5 GHz maximum clock frequency. The extracted offset shows a significant improvement of 78.5% over the conventional DLC. The die area of the circuit is about 108.54 mm 2 .