Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS

This article describes an architecture that autonomously sets the operating supply voltage (Vdd) of a digital system for minimum total energy dissipation, inclusive of regulator loss. The technique directly computes the energy per cycle (EPC) delivered by the supply to the system, to guide Vddadjustment for minimum energy-per-cycle point (MEP; voltage: VMEPand frequency: fMEP) tracking. The proposed approach avoids significant Vddmargins typically required for system operation near-threshold and at sub-threshold Vddlevels by employing a unified clock and power (UniCaP) architecture that regulates target performance across process, voltage, and temperature (PVT) variation with minimal guardband requirements. Measurement results from a 65-nm CMOS test chip demonstrate the VMEPtracking with less than 5 mV of error within the operating voltage range of 0.38-0.58 V. Measurement results also demonstrate the MEP tracking with temperature variation from -30 °C to 105 °C across varied loading conditions over 20 different test chips.