Exploration of Interplay Between Charge Trapping Dynamics and Polarization Switching in α -In₂Se₃ Ferroelectric Semiconductor FETs

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The trap behavior in a two-dimensional (2D) ferroelectric semiconductor (FeS) field-effect transistors (FETs) that can overcome the device scaling limit of conventional ferroelectric FETs was analyzed. The conventional ferroelectric FETs exhibit a counterclockwise hysteresis loop, whereas ferroelectric channel-based FETs with high effective oxide thickness exhibit a clockwise hysteresis loop. Therefore, it is challenging to determine the contribution of ferroelectric polarization switching and trap states to the current conduction of FeS-FETs and to quantify their respective impacts, owing to their complex interaction. The modified conductance method with a four-element equivalent circuit model was employed to analyze the behavior of intrinsic trap states, with parasitic capacitance de-embedded, depending on the FeS polarization switching states. As a result, we confirmed that over the full energy range trap density can be extracted by unique characteristics of FeS-FETs. The retention characteristic was maintained at over 70 % of the initial memory on/off ratio when extrapolated to 104s. Based on these results, guidelines for undefined trap state behavior of 2D α-In2Se3FeS-FETs were presented.