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September 17, 2014IEEE Journal of Solid-State Circuits

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

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Authors

TOTae-Young OhSamsung (South Korea)HCHoeju ChungSK Group (South Korea)JPJunyoung ParkKongju National University

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Oh et al. (2014) studied this question.

synapsesocial.com/papers/6a98fed17a0bd180b0e11661https://doi.org/10.1109/jssc.2014.2353799
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