Mixed‐Dimensional 1D/2D Ternary CMOS for High‐Performance Integrated Circuits

Ternary logic offers a path to higher information density and lower power consumption beyond the limits of binary CMOS, yet its progress has been limited by the absence of high‐performance ternary transistors and scalable circuit technologies. Here we report a mixed‐dimensional ternary CMOS (T‐CMOS) platform that monolithically integrates aligned carbon nanotubes (CNTs) and monolayer MoS 2 within silicon backend‐of‐line processes. The resulting CNT‐MoS 2 heterojunction transistors exhibit more than an order‐of‐magnitude performance improvement in output current and negative differential transconductance over previous ternary devices, enabling robust three‐level switching with large noise margins. By co‐fabricating CNT p‐FETs and MoS 2 n‐FETs into heterojunction devices, we realize CMOS‐compatible standard, positive and negative ternary inverters, as well as NMIN and NMAX logic gates. A fully functional ternary 2‐to‐9 decoder, the most complex low‐dimensional ternary circuit to date, is also demonstrated. Dynamic measurements and calibrated simulations confirm the scalability, cascade capability, and robustness of the T‐CMOS architecture, providing a viable pathway toward large‐scale ternary integrated circuits beyond binary limits.