Reconfigurable CMOS ternary inverter based on charge-trapping-enabled VTC modulation

A major challenge in complementary metal-oxide-semiconductor (CMOS)-based ternary inverters is achieving a balanced combination of power consumption, switching speed, functional flexibility, and compatibility with conventional CMOS technology. Despite various efforts, simultaneously achieving competitive power consumption, fast switching, and functional flexibility within a CMOS-compatible framework remains challenging. In this work, we propose a reconfigurable ternary inverter that leverages charge-trapping-layer (CTL)-induced threshold voltage ( V th ) modulation to enable controllable modulation of voltage transfer characteristics (VTC). By selectively integrating CTLs into different transistor types, we demonstrate that the VTC can be modulated either vertically or horizontally depending on the device location, enabling precise control of the intermediate logic level and switching boundaries. Based on this mechanism, the proposed inverter supports dynamic reconfiguration between ternary and binary operations through programmable V th tuning. The use of a silicon-oxide-nitride-oxide-silicon (SONOS) FinFET structure provides improved electrostatic control while maintaining compatibility with conventional Si CMOS technology. Through technology computer-aided design (TCAD)-based mixed-mode simulations calibrated with experimental data, we demonstrate that the CTL integration location strongly influences both VTC modulation and circuit performance. Among the investigated configurations, low-threshold-voltage transistor (LVT)-CTL integration enables binary/ternary reconfiguration while maintaining a VDD/2 power consumption of 173 nW and average propagation delays of 5.10 and 4.77 ns under ternary and binary operations, respectively. In contrast, the high-threshold-voltage transistor (HVT)-CTL integration exhibits a pronounced propagation-delay penalty under ternary operation, highlighting the importance of CTL placement in reconfigurable ternary inverter design. These results suggest a general design strategy for VTC engineering in multi-valued logic (MVL) circuits, in which CTL placement serves as a key design parameter for controlling the VTC modulation mode and associated circuit-performance trade-offs.